ABSTRACT
In recent years software network switches have regained eminence as a result of a number of growing trends, including the prominence of software-defined networks, as well as their use as back-ends to virtualization technologies, to name a few. Consequently, a number of high performance switches have been recently proposed in the literature, though none of these simultaneously provide (1) high packet rates, (2) high throughput, (3) low CPU usage, (4) high port density and (5) a flexible data plane. This is not by chance: these features conflict, and while achieving one or a few of them is (now) a solved problem, addressing the combination requires significant new design effort.
In this paper we fill the gap by presenting mSwitch. To prove the flexibility and performance of our approach, we use mSwitch to build four distinct modules: a learning bridge consisting of 45 lines of code that outperforms FreeBSD's bridge by up to 8 times; an accelerated Open vSwitch module requiring small changes to the code and boosting performance by 2.6--3 times; a protocol demultiplexer for userspace protocol stacks; and a filtering module that can direct packets to virtualized middleboxes.
- The netmap project. http://info.iet.unipi.it/~luigi/netmap/.Google Scholar
- M. Alizadeh, S. Yang, S. Katti, N. McKeown, B. Prabhakar, and S. Shenker. Deconstructing datacenter packet transport. In Proc. ACM HotNets, pages 133--138, 2012. Google ScholarDigital Library
- A. Belay, G. Prekas, A. Klimovic, S. Grossman, C. Kozyrakis, and E. Bugnion. Ix: A protected dataplane operating system for high throughput and low latency. In Proc. USENIX OSDI, pages 49--65, Oct. 2014. Google ScholarDigital Library
- Bob Jenkins' Web Site. SpookyHash: a 128-bit noncryptographic hash. http://www.burtleburtle.net/bob/hash/spooky.html, October 2013.Google Scholar
- M. Dobrescu, N. Egi, K. Argyraki, B.-G. Chun, K. Fall, G. Iannaccone, A. Knies, M. Manesh, and S. Ratnasamy. Routebricks: exploiting parallelism to scale software routers. In Proc. ACM SOSP, pages 15--28, 2009. Google ScholarDigital Library
- ETSI Portal. Network Functions Virtualisation: An Introduction, Benefits, Enablers, Challenges and Call for Action. http://portal.etsi.org/NFV/NFV_White_Paper.pdf, October 2012.Google Scholar
- S. Han, K. Jang, K. Park, and S. Moon. Packetshader: a gpu-accelerated software router. In Proc. ACM SIGCOMM, September 2010. Google ScholarDigital Library
- M. Honda, F. Huici, C. Raiciu, J. Araujo, and L. Rizzo. Rekindling network protocol innovation with user-level stacks. ACM CCR, 44(2): 52--58, Apr. 2014. Google ScholarDigital Library
- M. Honda, Y. Nishida, C. Raiciu, A. Greenhalgh, M. Handley, and H. Tokuda. Is it Still Possible to Extend TCP? In Proc. ACM IMC, pages 181--192, 2011. Google ScholarDigital Library
- J. Hwang, K. Ramakrishnan, and T. Wood. Netvm: high performance and flexible networking using virtualization on commodity platforms. In Proc. USENIX NSDI. Google ScholarDigital Library
- Intel. Intel DPDK: Data Plane Development Kit. http://dpdk.org, September 2013.Google Scholar
- Intel. Intel Ethernet Flow Director. http://www.intel.com/content/www/us/en/ethernet-controllers/ethernet-flow-director-video.html, May 2015.Google Scholar
- Intel Corporation. Packet Processing - Intel DPDK vSwitch - OVS. https://github.com/01org/dpdk-ovs, January 2014.Google Scholar
- J. Martins, M. Ahmed, C. Raiciu, V. Olteanu, M. Honda, R. Bifulco, and F. Huici. Clickos and the art of network function virtualization. In Proc. USENIX NSDI, pages 459--473, Apr. 2014. Google ScholarDigital Library
- NEC Laboratories Europe. Cloud Networking Performance Lab. http://cnp.neclab.eu/.Google Scholar
- OPEN VSWITCH. Open vSwitch. http://openvswitch.org, 2013.Google Scholar
- S. Peter, J. Li, I. Zhang, D. R. K. Ports, D. Woos, A. Krishnamurthy, T. Anderson, and T. Roscoe. Arrakis: The operating system is the control plane. In Proc. USENIX OSDI, pages 1--16, Oct. 2014. Google ScholarDigital Library
- K. K. Ram, A. L. Cox, and S. Rixner. Hyper-switch: A scalable software virtual switching architecture. In Proc. USENIX ATC, 2013. Google ScholarDigital Library
- L. Rizzo. netmap: a novel framework for fast packet I/O. In Proc. USENIX ATC, 2012. Google ScholarDigital Library
- L. Rizzo, M. Carbone, and G. Catalli. Transparent acceleration of software packet forwarding using netmap. In Proc. IEEE INFOCOM, pages 2471--2479, 2012.Google ScholarCross Ref
- L. Rizzo and G. Lettieri. Vale: a switched ethernet for virtual machines. In Proc. ACM CoNEXT, December 2012. Google ScholarDigital Library
- J. H. Salim, R. Olsson, and A. Kuznetsov. Beyond softnet. In Proc. USENIX Linux Showcase and Conference, 2001. Google ScholarDigital Library
- SDNCentral.com. Time for an SDN Sequel? Scott Shenker Preaches SDN Version 2. https://www.sdxcentral.com/articles/news/scott-shenker-preaches-revised-sdn-sdnv2/2014/10/, October 2014.Google Scholar
- V. Sekar, N. Egi, S. Ratnasamy, M. Reiter, and G. Shi. Design and implementation of a consolidated middlebox architecture. In Proc. USENIX NSDI, 2012. Google ScholarDigital Library
- J. Sherry, S. Hasan, C. Scott, A. Krishnamurthy, S. Ratnasamy, and V. Sekar. Making middleboxes someone else's problem: network processing as a cloud service. In Proc. ACM SIGCOMM, pages 13--24, 2012. Google ScholarDigital Library
- D. Zhou, B. Fan, H. Lim, D. G. Andersen, and M. Kaminsky. Scalable, high performance ethernet forwarding with cuckooswitch. In Proc. ACM CoNEXT, December 2013. Google ScholarDigital Library
Index Terms
- mSwitch: a highly-scalable, modular software switch
Recommendations
Analytical Modelling of Software and Hardware Switches with Internal Buffer in Software-Defined Networks
AbstractOpenFlow supports internal buffering of data packets in Software-Defined Networking (SDN) switch whereby a fraction of data packet header is sent to the controller instead of an entire data packet. This internal buffering increases the ...
Graphical abstractDisplay Omitted
Highlights- We propose a unified queues model for hardware and software SDN switch with internal buffer.
Twin peaks: a software platform for heterogeneous computing on general-purpose and graphics processors
PACT '10: Proceedings of the 19th international conference on Parallel architectures and compilation techniquesModern processors are evolving into hybrid, heterogeneous processors with both CPU and GPU cores used for general purpose computation. Several languages such as Brook, CUDA, and more recently OpenCL are being developed to fully harness the potential of ...
On the Programmability and Performance of Heterogeneous Platforms
ICPADS '13: Proceedings of the 2013 International Conference on Parallel and Distributed SystemsGeneral-purpose computing on an ever-broadening array of parallel devices has led to an increasingly complex and multi-dimensional landscape with respect to programmability and performance optimization. The growing diversity of parallel architectures ...
Comments