ABSTRACT
Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst-case access statistics, thereby resulting in very frequent refresh cycles, which are responsible for the majority of the standby power consumption of these memories. However, such a high refresh rate may not be required, either due to extremely low probability of the actual occurrence of such a worst-case, or due to the inherent error resilient nature of many applications that can tolerate a certain number of potential failures. In this paper, we exploit and quantify the possibilities that exist in dynamic memory design by shifting to the so-called approximate computing paradigm in order to save power and enhance yield at no cost. The statistical characteristics of the retention time in dynamic memories were revealed by studying a fabricated 2kb CMOS compatible embedded DRAM (eDRAM) memory array based on gain-cells. Measurements show that up to 73% of the retention power can be saved by altering the refresh time and setting it such that a small number of failures is allowed. We show that these savings can be further increased by utilizing known circuit techniques, such as body biasing, which can help, not only in extending, but also in preferably shaping the retention time distribution. Our approach is one of the first attempts to access the data integrity and energy trade-offs achieved in eDRAMs for utilizing them in error resilient applications and can prove helpful in the anticipated shift to approximate computing.
- "ITRS - 2013 edition," 2013. {Online}. Available: http://www.itrs.netGoogle Scholar
- D. Somasekhar et al., "2 GHz 2 Mb 2T gain cell memory macro with 128 GBytes/sec bandwidth in a 65 nm logic process technology," JSSC, vol. 44, no. 1, pp. 174--185, 2009.Google Scholar
- K. Chun et al., "A 667 MHz logic-compatible embedded DRAM featuring an asymmetric 2T gain cell for high speed on-die caches," JSSC, 2012.Google Scholar
- Y. S. Park et al., "Low-power high-throughput LDPC decoder using non-refresh embedded DRAM," JSSC, vol. 49, no. 3, pp. 783--794, 2014.Google Scholar
- A. Teman et al., "Replica technique for adaptive refresh timing of gain-cell-embedded DRAM," IEEE TCAS-II: Express Briefs, vol. 61, no. 4, pp. 259--263, April 2014.Google ScholarCross Ref
- P. Gupta et al., "Underdesigned and opportunistic computing in presence of hardware variability," IEEE TCAD, vol. 32, no. 1, pp. 8--23, 2013. Google ScholarDigital Library
- J. Henkel et al., "Multi-layer dependability: From microarchitecture to application level," in ACM-DAC '14, 2014, pp. 1--6. Google ScholarDigital Library
- S. Venkataramani et al., "Quality programmable vector processors for approximate computing," in IEEE/ACM ISM 2013, 2013, pp. 1--12. Google ScholarDigital Library
- S. Liu et al., "Flikker: Saving DRAM refresh-power through critical data partitioning," SIGPLAN Not., vol. 46, no. 3, pp. 213--224, Mar. 2011. Google ScholarDigital Library
- A. Sampson et al., "Approximate storage in solid-state memories," in Proceedings IEEE/ACM ISM '13, 2013, pp. 25--36. Google ScholarDigital Library
- Y. Lee et al., "A 5.42nW/kB retention power logic-compatible embedded DRAM with 2T dual-VT gain cell for low power sensing applicaions," in Proc. IEEE A-SSCC, 2010.Google Scholar
- P. Meinerzhagen et al., "Impact of body biasing on the retention time of gain-cell memories," IET JoE, vol. 1, no. 1, 2013.Google Scholar
- L. Tran et al., "Heterogeneous memory management for 3D-DRAM and external DRAM with QoS," in ASP-DAC '13, 2013, pp. 663--668.Google Scholar
- R. Giterman et al., "4T gain-cell with internal-feedback for ultra-low retention power at scaled CMOS nodes," in Proc. IEEE ISCAS 2014.Google Scholar
- M. S. Khairy et al., "Algorithms and architectures of energy-efficient error-resilient MIMO detectors for memory-dominated wireless communication systems," IEEE TCAS-I, vol. 61-I, no. 7, 2014.Google Scholar
- H. Cho et al., "ERSA: error resilient system architecture for probabilistic applications," IEEE TCAD, vol. 31, no. 4, pp. 546--558, 2012. Google ScholarDigital Library
- V. K. Chippa et al., "Analysis and characterization of inherent application resilience for approximate computing," in ACM-DAC '13, 2013. Google ScholarDigital Library
- G. Karakonstantis et al., "On the exploitation of the inherent error resilience of wireless systems under unreliable silicon," in ACM-DAC '12, 2012, pp. 510--515. Google ScholarDigital Library
Index Terms
- Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories
Recommendations
Nanoscale Memories Pose Unique Challenges
This special issue presents seven articles that examine the characteristics, capabilities, and challenges of various embedded memories, especially those designed in emerging technologies. The articles address the intricacies and trade-offs required by ...
Embedded Memories: Progress and a Look into the Future
Memories are categorized as embedded memories (e-memories) and stand-alone memories. E-memories favor high speed rather than low cost. In addition, they must maintain compatibility with the logic process, because they must be cofabricated on the same ...
Reducing cache power with low-cost, multi-bit error-correcting codes
ISCA '10: Proceedings of the 37th annual international symposium on Computer architectureTechnology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically refreshed to retain data. Like SRAM, eDRAM is susceptible to device ...
Comments