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SimPL: an algorithm for placing VLSI circuits

Published:01 June 2013Publication History
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Abstract

VLSI placement optimizes locations of circuit components so as to reduce interconnect. Formulated in terms of (hyper) graphs, it is NP-hard, and yet must be solved for challenging million-node instances within several hours. We propose an algorithm for large-scale placement that outperforms prior art both in runtime and solution quality on standard benchmarks. The algorithm is more straightforward than existing placers and easier to integrate into timing-closure flows. Our C++ implementation is compact, self-contained and exploits instruction-level and thread-level parallelism. Due to its simplicity and superior performance, the algorithm has been adopted in the industry and was extended by several university groups to multi-objective optimization.

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          cover image Communications of the ACM
          Communications of the ACM  Volume 56, Issue 6
          June 2013
          104 pages
          ISSN:0001-0782
          EISSN:1557-7317
          DOI:10.1145/2461256
          Issue’s Table of Contents

          Copyright © 2013 ACM

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          • Published: 1 June 2013

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