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Using simple abstraction to reinvent computing for parallelism

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Published:01 January 2011Publication History
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Abstract

The ICE abstraction may take CS from serial (single-core) computing to effective parallel (many-core) computing.

References

  1. Adve, S. et al. Parallel Computing Research at Illinois: The UPCRC Agenda. White Paper. University of Illinois, Champaign-Urbana, IL,2008; http://www.upcrc.illinois.edu/UPCRC_Whitepaper.pdfGoogle ScholarGoogle Scholar
  2. Asanovic, K. et al. The Landscape of Parallel Computing Research: A View from Berkeley. Technical Report UCB/EECS-2006-183. University of California, Berkeley, 2006; http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-183.pdfGoogle ScholarGoogle Scholar
  3. Balkan, A., Horak, M., Qu, G., and Vishkin, U. Layout-accurate design and implementation of a high-throughput interconnection network for single-chip parallel processing. In Proceedings of the 15th Annual IEEE Symposium on High Performance Interconnects (Stanford, CA, Aug. 22--24). IEEE Press, Los Alamitos, CA, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Blake, G., Dreslinski, R., Flautner, K., and Mudge, T. Evolution of thread-level parallelism in desktop applications. In Proceedings of the 37th Annual International Symposium on Computer Architecture (Saint-Malo, France, June 19--23). ACM Press, New York, 2010, 302--313. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Borkar, S. et al. Platform 2015: Intel Processor and Platform Evolution for the Next Decade. White Paper. Intel, Santa Clara, CA, 2005; http://epic.hpi.unipotsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdfGoogle ScholarGoogle Scholar
  6. Caragea, G., Tzannes, A., Keceli, F., Barua, R., and Vishkin, U. Resource-aware compiler prefetching for many-cores. In Proceedings of the Ninth International Symposium on Parallel and Distributed Computing (Istanbul, Turkey, July 7--9). IEEE Press, Los Alamitos, CA, 2010, 133--140. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Caragea, G., Keceli, F., Tzannes, A., and Vishkin, U. General-purpose vs. GPU: Comparison of many-cores on irregular workloads. In Proceedings of the Second Usenix Workshop on Hot Topics in Parallelism (University of California, Berkeley, June 14--15). Usenix, Berkeley, CA, 2010.Google ScholarGoogle Scholar
  8. Caragea, G., Saybasili, B., Wen, X., and Vishkin, U. Performance potential of an easy-to-program PRAM-on-chip prototype versus state-of-the-art processor. In Proceedings of the 21st ACM SPAA Symposium on Parallelism in Algorithms and Architectures (Calgary) Canada, Aug. 11--13). ACM Press, New York, 2009, 163--165. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Cormen, T., Leiserson, C., Rivest, R., and Stein, C. Introduction to Algorithms, Third Edition. MIT Press, Cambridge, MA, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Culler, D. and Singh, J. Parallel Computer Architecture: A Hardware/Software Approach. Morgan-Kaufmann, San Francisco, CA, 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Gibbons, P., Matias, Y., and Ramachandran, V. The queue-read queue-write asynchronous PRAM model. Theoretical Computer Science 196, 1--2 (Apr. 1998), 3--29. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Gottlieb, A. et al. The NYU ultracomputer designing an MIMD shared-memory parallel computer. IEEE Transactions on Computers 32, 2 (Feb. 1983), 175--189. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Gu, P. and Vishkin, U. Case study of gate-level logic simulation on an extremely fine-grained chip multiprocessor. Journal of Embedded Computing 2, 2 (Apr. 2006), 181--190. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Hochstein, L., Basili, V., Vishkin, U., and Gilbert, J. A pilot study to compare programming effort for two parallel programming models. Journal of Systems and Software 81, 11 (Nov. 2008), 1920--1930. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Horak, M., Nowick, S., Carlberg, M., and Vishkin, U. A low-overhead asynchronous interconnection network for gals chip multiprocessor. In Proceedings of the Fourth ACM/IEEE International Symposium on Networks-on-Chip (Grenoble, France, May 3--6). IEEE Computer Society, Washington D.C., 2010, 43--50. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. JaJa, J. An Introduction to Parallel Algorithms. Addison-Wesley Publishing Company, Reading, MA, 1992. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Keller, J., Kessler, C., and Traeff, J. Practical PRAM Programming. Wiley-Interscience, New York, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Nuzman, J. and Vishkin, U. Circuit Architecture for Reduced-Synchrony-On-Chip Interconnect. U.S. Patent 6,768,336, 2004; http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=6768336.PN.&OS=PN/6768336&RS=PN/6768336Google ScholarGoogle Scholar
  19. Patterson, D. The trouble with multi-core: Chipmakers are busy designing microprocessors that most programmers can't handle. IEEE Spectrum (July 2010). Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Shiloach, Y. and Vishkin, U. An O(n 2 log n) parallel max-flow algorithm. Journal of Algorithms 3, 2 (Feb.1982), 128--146. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Sutter, H. The free lunch is over: A fundamental shift towards concurrency in software. Dr. Dobb's Journal 30, 3 (Mar. 2005).Google ScholarGoogle Scholar
  22. Torbert, S., Vishkin, U., Tzur, R., and Ellison, D. Is teaching parallel algorithmic thinking to high school students possible? One teacher's experience. In Proceedings of the 41st ACM Technical Symposium on Computer Science Education (Milwaukee, WI, Mar. 10--13). ACM Press, New York, 2010, 290--294. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Tzannes, A., Caragea, G., Barua, R., and Vishkin, U. Lazy binary splitting: A run-time adaptive dynamic works-stealing scheduler. In Proceedings of the 15th ACM Symposium on Principles and Practice of Parallel Programming (Bangalore, India, Jan. 9--14). ACM Press, New York, 2010, 179--189. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Valiant, L. A bridging model for multi-core computing. In Proceedings of the European Symposium on Algorithms (Karlruhe, Germany, Sept. 15--17). Lecture Notes in Computer Science 5193. Springer, Berlin, 2008, 13--28. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Vishkin, U. U.S. Patents 6,463,527; 6,542,918; 7,505,822; 7,523,293; 7,707,388, 2002--2010; http://patft.uspto.gov/Google ScholarGoogle Scholar
  26. Vishkin, U. Algorithmic approach to designing an easy-to-program system: Can it lead to a hardware-enhanced programmer's workflow add-on? In Proceedings of the 27th International Conference on Computer Design (Lake Tahoe, CA, Oct. 4--7). IEEE Computer Society, Washington D.C., 2009, 60--63. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Vishkin, U., Caragea, G., and Lee, B. Models for advancing PRAM and other algorithms into parallel programs for a PRAM-on-chip platform. In Handbook on Parallel Computing, S. Rajasekaran and J. Reif, Eds. Chapman and Hall/CRC Press, Boca Raton, FL, 2008, 5.1--60.Google ScholarGoogle Scholar
  28. Wen, X. and Vishkin, U. FPGA-based prototype of a PRAM-on-chip processor. In Proceedings of the Fifth ACM Conference on Computing Frontiers (Ischia, Italy, May 5--7). ACM Press, New York, 2008, 55--66. Google ScholarGoogle ScholarDigital LibraryDigital Library

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                cover image Communications of the ACM
                Communications of the ACM  Volume 54, Issue 1
                January 2011
                128 pages
                ISSN:0001-0782
                EISSN:1557-7317
                DOI:10.1145/1866739
                Issue’s Table of Contents

                Copyright © 2011 ACM

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                Publication History

                • Published: 1 January 2011

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