In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

ABSTRACT

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

References

1. Kaenel, V. et al, "Automatic Adjustment of Threshold & Supply Voltages for minimum power consumption in CMOS Digital Circuits", IEEE International Symposium on Low power electronics, 1994
2. Nomura, M. et al., "Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes," Solid-State Circuits, IEEE Journal of, vol.41, no.4, pp. 805--814, April 2006
3. Kao, J.T. et al., "A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture," Solid-State Circuits, IEEE Journal of, vol.37, no.11, pp. 1545--1554, Nov 2002
4. Kuroda, T. et al., "Variable supply-voltage scheme for low-power high-speed CMOS digital design," Solid-State Circuits, IEEE Journal of, vol.33, no.3, pp.454--462, Mar 1998
5. Koichi Nose et al., "Optimization of VDD and VTH for low-power and high speed applications," ASP-DAC 2000, 469--474
6. K. Roy, et al., "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer cmos circuits," Proceedings of the IEEE, vol. 91, no. 2, pp. 305--327, April 2003.
7. Dongwoo, L. et al., "Gate oxide leakage current analysis and reduction for VLSI circuits", IEEE Transaction on Very Large Scale Integration, Vol. 12, No. 2, Feb. 2004
8. Markovic, D. et al., "Methods for true energy-performance optimization," Solid-State Circuits, IEEE Journal of, vol.39, no.8, pp. 1282--1293, Aug. 2004
9. Jotwani, R. et al., "An x86-64 core implemented in 32nm SOI CMOS", IEEE International Solid State Circuit Conference, 2010
10. Ramadass, Y.K. et al., "Minimum Energy Tracking Loop With Embedded DC-DC Converter Enabling Ultra-Low-Voltage Operation Down to 250 mV in 65 nm CMOS," Solid-State Circuits, IEEE Journal of, vol.43, no.1, pp.256--265, Jan. 2008
11. McGowen, R. et al., "Power and temperature control on a 90-nm Itanium family processor," Solid-State Circuits, IEEE Journal of, vol.41, no.1, pp. 229--237, Jan. 2006
12. K Sreejith et al., "A Workload Based Lookup table for minimal power operation under supply and body bias control", Journal of Low Power Electronics, August 2009.
13. Zhai, B. et al., "Theoretical and practical limits of dynamic voltage scaling." In Proceedings of the 41st Annual Design Automation Conference DAC '04.
14. Tschanz, J. et al., "Dynamic sleep transistor and body bias for active leakage power control of microprocessors," Solid-State Circuits, IEEE Journal of, vol.38, no.11, pp. 1838- 1845, Nov. 2003
15. Wang, A. et al., "Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits" In Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2002.
16. Nakai, M. et al., "Dynamic voltage and frequency management for a low-power embedded microprocessor," Solid-State Circuits, IEEE Journal of, vol.40, no.1, pp. 28- 35, Jan. 2005
17. Kim, S. et al, "Understanding and minimizing ground bounce during mode transition of power gating structures". In Proceedings of the 2003 international Symposium on Low Power Electronics and Design. ISLPED '03. ACM, New York, 22--25.
18. Naffziger, S. "Sampling chip activity for real time power estimation", US patent 2009/0259869A1

Index Terms

• Hardware

  • Very large scale integration design

    • Application-specific VLSI designs

      • Application specific processors