Fast instruction cache modeling for approximate timed HW/SW co-simulation

ABSTRACT

Approximate timed co-simulation has been proposed as a fast solution for system modeling in early design steps. This co-simulation technique enables the simulation of systems at speeds close to functional execution, while considering timing effects. As a consequence, system performance estimations can be obtained early, enabling efficient design space exploration and system refinement. To achieve fast simulation speeds, first the SW code is pre-annotated with time information and then it is natively executed, performing what is called native-based co-simulation. To obtain sufficiently accurate performance estimations, the effect of the system components must be considered. Among them, processor caches are really important, as they have a strong impact on the overall system performance. However, no efficient techniques for cache modeling in native-based co-simulation have been proposed. Previous works considering caches apply slow cache models based on tag search, similar to ISS-based models. This solution slows down the simulation speed, greatly reducing the efficiency of native based co-simulations. In this paper, a high-level instruction cache model is proposed, along with the required instrumentation for native simulation. This model allows the designer to obtain cache hit/miss rate estimations with simulation speeds very close to native execution. Results present a speed-up of two orders of magnitude with respect to ISS and one order of magnitude regarding previous approaches in native simulation. Miss rate estimation error remains below 5%.

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Index Terms

• Hardware

  • Hardware validation