FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation

ABSTRACT

Glitches (i.e. spurious signal transitions) are major sources of dynamic power consumption in modern FPGAs. In this paper, we present an FPGA-targeted, glitch-aware, high-level binding algorithm for power and area reduction, accomplished via dynamic power estimation and multiplexer balancing. Our binding algorithm employs a glitch-aware dynamic power estimation technique derived from the FPGA technology mapper in [6]. High-level binding results are converted to VHDL, and synthesized with Altera's Quartus II software, targeting the Cyclone II FPGA architecture. Power characteristics are evaluated with the Altera Power-Play Power Analyzer. The binding results of our algorithm are compared to LOPASS, a state-of-the-art low-power high-level synthesis algorithm for FPGAs. Experimental results show that our algorithm, on average, reduces toggle rate by 22% and area by 9%, resulting in a decrease in dynamic power consumption of 19%. To the best of our knowledge this is the first high-level binding algorithm targeting FP-GAs that considers glitch power.

References

1. J.-M. Chang and M. Pedram. Register allocation and binding for low power. DAC, 1995.
2. D. Chen and J. Cong. Register binding and port assignment for multiplexer optimization. ASP-DAC, 2004.
3. D. Chen, J. Cong, and Y. Fan. Low-power high-level synthesis for FPGA architectures. In ISLPED, 2003.
4. D. Chen, J. Cong, Y. Fan, and L. Wan. LOPASS: A low-power architectural synthesis system for FPGAs with interconnect estimation and optimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, to be published.
5. D. Chen, J. Cong, Y. Fan, and Z. Zhang. High-level power estimation and low-power design space exploration for FPGAs. In ASP-DAC, 2007.
6. L. Cheng, D. Chen, and M. D. F. Wong. GlitchMap: an FPGA technology mapper for low power considering glitches. In DAC, 2007.
7. T.-L. Chou and K. Roy. Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(10):1257--1265, Oct. 1996.
8. J. Cong, C. Wu, and Y. Ding. Cut ranking and pruning: enabling a general and efficient FPGA mapping solution. In FPGA, 1999.
9. A. Dasgupta and R. Karri. Simultaneous scheduling and binding for power minimization during microarchitecture synthesis. In ISLPED, 1995.
10. A. Davoodi and A. Srivastava. Effective techniques for the generalized low-power binding problem. ACM Trans. Des. Autom. Electron. Syst., 11(1):52--69, 2006.
11. C.-Y. Huang, Y.-S. Chen, Y.-L. Lin, and Y.-C. Hsu. Data path allocation based on bipartite weighted matching. DAC, 1990.
12. B. Krishnamurthy and I. Tollis. Improved techniques for estimating signal probabilities. IEEE Transactions on Computers, 38(7):1041--1045, Jul. 1989.
13. I. Kuon and J. Rose. Measuring the gap between FPGAs and ASICs. In FPGA, 2006.
14. E. Kursun, A. Srivastava, S. O. Memik, and M. Sarrafzadeh. Early evaluation techniques for low power binding. In ISLPED, 2002.
15. J. Lamoureux, G. G. Lemieux, and S. J. E. Wilton. GlitchLess: an active glitch minimization technique for FPGAs. In FPGA, 2007.
16. F. Li, Y. Lin, L. He, D. Chen, and J. Cong. Power modeling and characteristics of field programmable gate arrays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(11):1712--1724, Nov. 2005.
17. F. Najm. Transition density: a new measure of activity in digital circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(2):310--323, Feb. 1993.
18. B. Pangrle. On the complexity of connectivity binding. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 10(11):1460--1465, Nov. 1991.
19. E. Sentovich, et al. SIS: A system for sequential circuit synthesis. Technical report, UCB/ERL Memorandum M89/49, Department of EECS, University of California, Berkeley, Nov. 1992.
20. F. Wolff, M. Knieser, D. Weyer, and C. Papachristou. High-level low power FPGA design methodology. NAECON, 2000.

Index Terms

• Hardware

  • Electronic design automation

    • Logic synthesis

      • Circuit optimization