T. M. McWilliams
ABSTRACT
In this article we give the design and evaluation of the CMU-11: a fully operational implementation of the PDP-11 computer architecture built with Intel 3000 Schottky bipolar microcomputer bit-slices. This project was initiated to test in detail the claims that LSI processor bit-slices simplify the design of microprogrammed processors. The CMU-11 executes approximately 240,000 instructions per second, which is about 63 percent the speed of the PDP-11/40 and twice the speed of the LSI-11.
We explore in some detail the additional logic that was added to enable the Intel 3000 circuits to emulate the PDP-11 instruction set. We specified full DEC Unibus compatibility and 29 percent of the integrated circuits used to implement the CMU-11 were required to provide buffering and control of the Unibus. The other main sources of inefficiency were the lack of arithmetic overflow logic in the bit-slices and the organization of the microinstruction control store. We show how improved LSI circuits in this area can substantially reduce the size (and cost) of the processor.
The set of design aids currently available at Carnegie-Mellon University was of critical assistance in this project and we include a critique of our use of these design aids to show their utility in prototype design efforts.
- Intel Schottky Bipolar LSI Microcomputer Set: 3001 Microprogram Control Unit, 3002 Control Progressive, Element, and 3003 Carry Lookahead Generator, Intel Corporation, Santa Clara, California, 1975.Google Scholar
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- Am2900 Bipolar Microprocessor Circuits, Advanced Micro Devices, Inc., Sunnyvale, California, 1975.Google Scholar
- Fuller, S. H., T. McWilliams, and W. Sherwood, CMU-11 Engineering Documentation, Department of Computer Science, Carnegie-Mellon University, Pittsburgh, Pa., 1976.Google Scholar
- PDP-11/05/10/35/40 Processor Handbook, Digital Equipment Corporation, Maynard, Mass., 1973.Google Scholar
- Using LSI processor bit-slices to build a PDP-11: a case study in microcomputer design
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