Virginia Escuder
ABSTRACT
The design of instruction sets is a fundamental aspect of computer architecture. A critical requirement of instruction set design is to allow for concurrent execution, avoiding those constructs that may produce data dependencies among instructions. Therefore, it is important to count on methods and tools for the evaluation of the behavior of instruction sets and quantify the influence of particular features of its architecture into the overall available parallelism. We propose an analysis method that applies graph theory to gather metrics to evaluate the impact of different characteristics of instruction sets as sources of coupling thus quantifying available parallelism. We present a case study using the x86 instruction set and obtain some measures of the influence of condition flags in code coupling.
- {1} T.L. Adams and R. E. Zimmerman, An analysis of 8086 instruction set usage in MS DOS programs, Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, 1989, pp. 152-160. Google Scholar
- {2} D. Clark and H. Levy, Measurement and analysis of instruction set use in the VAX-11/780, Proceedings of the 9th Symposium on Computer Architecture, 1982, pp. 9-17. Google Scholar
- {3} R. Durán and R. Rico, On Applying Graph Theory to ILP Analysis, Technical Note TN-UAH-AUTGAP-2005-01 , 2005, (http://atc2.aut.uah.es/~gap).Google Scholar
- {4} R. Durán and R. Rico, Quantification of ISA Impact on Superscalar Processing, Proceeding of EUROCON 2005, 2005, pp. 701-704.Google Scholar
- {5} I. J. Huang and T. C. Peng, Analysis of x86 Instruction Set Usage for DOS/Windows Applications and Its Implication on Superscalar Design, IEICE Transactions on Information and Systems, Vol. E85-D, No. 6, 2002, pp. 929-939.Google Scholar
- {6} R. Rico, Proposal of test-bench for the x86 instruction set (16 bits subset), Technical Report TR-UAH-AUTGAP-2005-21 , 2005, (http://atc2.aut.uah.es/~gap).Google Scholar
- {7} R. Rico, et al., The impact of x86 instruction set architecture on superscalar processing, Journal of Systems Architecture, vol. 51-1, 2005, pp. 63-77. Google Scholar
- {8} D. W. Wall, Limits of instruction-level parallelism, Proc. of 4th Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, 1991, pp. 176-188. Google Scholar
- {9} Software tool (source code, configuration files, documentation): data dependence analyzer ADD; CVS repository (anonymous user): CVSROOOT:pserver:[email protected]:2 401/home/cvsmgr/repositorioGoogle Scholar
Index Terms
- Evaluating x86 condition codes impact on superscalar execution
Recommendations
The impact of x86 instruction set architecture on superscalar processing
Performance improvement of x86 processors is a relevant matter. From the point of view of superscalar processing, it is necessary to complement the studies on instruction use with analogous ones on data use and, furthermore, analyze the data flow graphs,...
Analysis of x86 ISA Condition Codes Influence on Superscalar Execution
High Performance Computing – HiPC 2007AbstractInstruction sets may have particular characteristics that produce a negative impact into the amount of available parallelism. The x86 instruction set architecture includes some of those characteristics. In particular, it is well know the negative ...
Analysis of x86 ISA condition codes influence on superscalar execution
HiPC'07: Proceedings of the 14th international conference on High performance computingInstruction sets may have particular characteristics that produce a negative impact into the amount of available parallelism. The x86 instruction set architecture includes some of those characteristics. In particular, it is well know the negative impact ...
Comments