ABSTRACT
Higher integration density of nanoscale CMOS causes two major design challenges in SRAM-based Field Programmable Gate Array (FPGA) designs: large power dissipation (contributed by both leakage and dynamic power) and reduced reliability of operation. In this paper, we propose a hybrid design approach for SRAM-based FPGA that can leverage on non-volatile carbon nanotube based nano electro-mechanical systems (NEMS) switches for low static and dynamic power. Simulations show that the proposed CMOS-NEMS lookup table (LUT) based circuits can achieve a reduction of up to 91% in total power at iso-performance, compared to the conventional CMOS-based LUT circuits.
- S. Hauck, "The roles of FPGAs in reprogrammable systems", Proceedings of the IEEE, pp. 615--638, 1998.Google ScholarCross Ref
- M. Orlowski, "CMOS challenges of keeping up with Moore's Law", RTP, pp. 3--21, 2005.Google Scholar
- K. Morris, "Power, Suddenly We Care", FPGA and Programmable Logic Journal, 2005.Google Scholar
- T. Rueckes et al., "Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing" Sciencemag, vol. 289 2000.Google Scholar
- E. Dujardin et al., "Self-assembled switches based on electroactuated multiwalled nanotubes", Appl. Phys .Lett., 87, 193107-1, 2005.Google Scholar
- S. W. Lee et al., "A Three-Terminal Carbon Nanorelay", Appl. Phys. A, 78, 283, 2004.Google ScholarCross Ref
- W. Liang et al., "Fabry-Perot interference in a nanotube electron waveguide", Nature 411, pp. 665--669, 2001.Google ScholarCross Ref
- A. Jungen et al., "Localized and CMOS compatible growth of carbon nanotubes on a 3X3 μm2 microheater spot", Digest of Tech. Papers, TRANSDUCERS, pp. 93--96, 2005.Google Scholar
- A. Raychowdhury and K. Roy, "Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies", IEEE TCAD, Vol. 25, Issue 1, pp. 58--65, 2006. Google ScholarDigital Library
- N. Srivastava and K. Banerjee, "Performance analysis of carbon nanotube interconnects for VLSI applications", ICCAD, pp. 383--390, 2005. Google ScholarDigital Library
- P. J. Burke, "An RF Circuit Model for Carbon Nanotubes," IEEE Tran. Nanotechnology, vol.2, no.1, March 2003. Google ScholarDigital Library
- P. L. McEuen et al., "Single-Walled Carbon Nanotube Electronics," IEEE Trans. Nanotechnology, Vol. 1, No. 1, pp. 78--85, 2000. Google ScholarDigital Library
- http://www-device.eecs.berkeley.edu/~ptm/Google Scholar
- A. Lodi et al., "Low leakage design of LUT-based FPGAs", Solid-State Circuits Conference, 2005.Google ScholarCross Ref
Index Terms
- Low power FPGA design using hybrid CMOS-NEMS approach
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