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Median and morphological specialized processors for a real-time image data processing

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Published:01 January 2002Publication History
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Abstract

This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author's earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.

References

  1. {1} P. Chalermwat, N. Alexandridis, P. Piamsa-Nga, and M. O'Connell, "Parallel image processing in heterogeneous computing network systems," in Proceedings of the IEEE International Conference on Image Processing (ICIP96), Lausanne, Switzerland, September 1996, pp. 16-19.Google ScholarGoogle Scholar
  2. {2} C. L. Wang, P. B. Bhat, and V. K. Prasanna, "High-performance computing for vision," in Proceedings of the IEEE, vol. 84, pp. 931-946, July 1996.Google ScholarGoogle ScholarCross RefCross Ref
  3. {3} XILINX, "The programmable logic data book," Xilinx Inc., 1999, San Jose, CA.Google ScholarGoogle Scholar
  4. {4} R. Duncan, "A survey of parallel computer architectures," Computer , vol. 23, no. 2, pp. 5-16, 1990. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. {5} A. Antola, A. Avai, and L. Breveglieri, "Modular design methodologies for image processing architectures," IEEE Trans. on VLSI Systems, vol. 1, no. 4, pp. 408-414, 1993.Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. {6} A. Kundu and J. Zhou, "Combination median filter," IEEE Trans. Image Processing, vol. 1, no. 3, pp. 422-429, 1992.Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. {7} G. Qiu, "An improved recursive median filtering scheme for image processing," IEEE Trans. Image Processing, vol. 5, no. 4, pp. 646-648, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. {8} X. Yang and P. S. Toh, "Adaptive fuzzy multilevel median filter," IEEE Transactions on Image Processing, vol. 4, no. 5, pp. 680-682, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. {9} B. Zeng, "Convergence properties of median and weighted median filters," IEEE Trans. on Signal Processing, vol. SP-42, no. 12, pp. 3515-3518, 1994.Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. {10} F. Cheng and A. N. Venetsanopoulos, "An adaptive morphological filter for image processing," IEEE Trans. Image Processing, vol. 1, no. 4, pp. 533-539, 1992.Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. {11} H. J. A. M. Heijmans, "Composing morphological filters," IEEE Trans. Image Processing, vol. 6, no. 5, pp. 713-723, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. {12} X. C. Jin, S. H. Ong, and Jayasooriah, "A domain operator for binary morphological processing," IEEE Trans. Image Processing , vol. 4, no. 7, pp. 1042-1046, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. {13} P. Maragos, "Differential morphology and image processing," IEEE Trans. Image Processing, vol. 5, no. 6, pp. 922-937, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. {14} P. J. Bakkes, J. J. du Plessis, and B. L. Hutchings, "Mixing fixed and reconfigurable logic for array processing," in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, April 1996, pp. 118-125.Google ScholarGoogle Scholar
  15. {15} W. Luk, N. Shirazi, and P. Y. K. Cheung, "Modeling and optimizing run-time reconfigurable systems," in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, California, November 1996, pp. 167-177.Google ScholarGoogle Scholar
  16. {16} J. Villasenor, C. Jones, and B. Schoner, "Video communications using rapidly reconfigurable hardware," IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 6, pp. 565-567, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. {17} K. Wiatr, "Specialized architecture of dedicated hardware processors for a real-time image data pre-processing," in Proceedings of the EUROMICRO International Conference: Real-Time Systems, Toledo, 1997.Google ScholarGoogle Scholar
  18. {18} UWICL, "UWICL 3.0 function list and performance figures," University of Washington Image Computing Library, http://icsl.ee.washington.edu/projects/iclib/.Google ScholarGoogle Scholar
  19. {19} CORECO, "Mamba benchmarks," Coreco Inc., 2000, St-Laurent, Quebec.Google ScholarGoogle Scholar

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  1. Median and morphological specialized processors for a real-time image data processing

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